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Double Buffered Read Interface

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Product Category :    Electronic Components and Devices

Supplier                :    System Automation Group

Key Features of Double Buffered Read Interface

  • The data bus may be of any width, from a one bit serial to parallel of any width.
  • The data to be loaded from the data bus may be of any width.
  • May be cascaded to others within the mega function.


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Product Profile of Double Buffered Read Interface

System Automation Group supplies Double Buffered Read Interface. System Automation Group offers a wide range of software and automation products like CPU, FPU, PLC, AC/DC Motor Control, communication chips, display controllers and peripherals. The Double Buffered Read Interface is used for interfacing intellectual property mega functions requiring data writing to a CPU data bus, for implementation in FPGA, ASIC and CPLD, VLSI devices.

Key Features of Double Buffered Read Interface
  • The data bus may be of any width, from a one bit serial to parallel of any width.
  • The data to be loaded from the data bus may be of any width.
  • May be cascaded to others within the mega function.
  • Multiple mega functions may be cascaded together on shared address, data and chip-select lines.
  • A FIFO buffer maximizes throughput and can be implemented in memory or registers.
  • Timing parameters enable it to be customised to any output constraints.
  • Generates Chip-selects that enable CPU interfacing to synchronous/asynchronous memories & mega functions
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